About Me
Since 2024, I am a fast-track PhD student at the Security Engineering group of Tim Güneysu at Ruhr University Bochum.
I obtained my B.Sc. in IT-Security from Ruhr University in 2023 and my M.Sc. in IT-Security in 2026. Previously, I was a working student in the Hardware Evaluation department of TÜVIT with a focus on the development of novel and efficient side-channel analysis software.
Contact
- Email: niklas@hoeher.dev
- GPG: B65B B466 6570 5BE8 8CCA AF4B 6B10 FBFE CB33 6ACC
- Misc: GitHub, Google Scholar, ORCID
Research Interests
- Security-aware Electronic Design Automation (EDA) tooling
- Efficient implementation of Post-Quantum Cryptography (PQC) in hardware
- Practical realization of combined Side-Channel Analysis (SCA) and Fault Injection (FI) attacks
Publications
| Venue | Title | Authors | Links |
|---|---|---|---|
| [In submission] | Storing Less in-the-Head: An Area-Efficient Hardware Architecture for SDitH-v2 | Stef Halmans, Niklas Höher, Dina Hesse, Sanjay Deshpande, Jakub Szefer, Tim Güneysu | [preprint] |
| TCHES 2026/3 | LFSRs and Boolean Masking: An In-depth Security Analysis | Anna Guinet, Jan Schoone, Niklas Höher, Dina Hesse, Tim Güneysu | |
| TCHES 2025/4 | HADES: Automated Hardware Design Exploration for Cryptographic Primitives | Fabian Buschkowski, Georg Land, Niklas Höher, Jan Richter-Brockmann, Pascal Sasdrich, Tim Güneysu | [paper] [preprint] [code] |
Awards
- Best IT-Security Master's graduate of the academic year 2025/2026 at Ruhr University Bochum
- Best IT-Security Bachelor's graduate of the academic year 2023/2024 at Ruhr University Bochum
Teaching
- Instructor Open-Source Chip Design Lab Course (winter term 2025/26)
- Teaching assistant Physical Attacks and Countermeasures (summer term 2025, summer term 2026)
- Teaching assistant Provable Security (summer term 2025)
- Teaching assistant Cryptography on Reconfigurable Hardware (winter term 2024/25, winter term 2025/26)
- Seminar Security Engineering (each term since 10/2024)
Reviewing and Subreviewing
- CHES 2026
- DATE 2026
- Asiacrypt 2025
Other Projects
- rijndael-sv: Configurable SystemVerilog implementation of the complete Rijndael proposal, including non-standardized variants (e.g., Rijndael-256-256)
- Co-creator of the OCDCpro student chip design competition funded by the German Federal Ministry of Research, Technology and Space